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19-2952; Rev 0; 7/03
Octal, 13-Bit Voltage-Output DAC with Parallel Interface
General Description
The MX7839 contains eight 13-bit, voltage-output digitalto-analog converters (DACs). On-chip precision output amplifiers provide the voltage outputs. The device operates from 15V supplies. Its bipolar output voltage swing is 10V and is achieved with no external components. The MX7839 has three pairs of differential reference inputs; two of these pairs are connected to two DACs each, and a third pair is connected to four DACs. The references are independently controlled, providing different full-scale output voltages to the respective DACs. The MX7839 features double-buffered interface logic with a 13-bit parallel data bus. Each DAC has an input latch and a DAC latch. Data in the DAC latch sets the output voltage. The eight input latches are addressed with three address lines. Data is loaded to the input latch with a single write instruction. An asynchronous load input (LDAC) transfers data from the input latch to the DAC latch. The LDAC input controls all DACs; therefore, all DACs can be updated simultaneously by asserting LDAC. An asynchronous CLR input sets the output of all eight DACs to the respective DUTGND input of the op amp. Note that CLR is a CMOS input, which is powered by VDD. All other logic inputs are TTL/CMOS compatible. The MX7839 is pin-for-pin compatible with AD7839. o Eight DACs in a Single Package o Buffered Voltage Outputs o Unipolar or Bipolar Voltage Swing to 10V o 31s Output Settling Time o Low Power Consumption: 8mA (typ) o Small 44-Pin MQFP Package o Double-Buffered Digital Inputs o Asynchronous Load Updates All DACs Simultaneously o Asynchronous CLR Forces All DACs to DUTGND_ _ Potential
Features
o Full 13-Bit Performance without Adjustments
MX7839
Ordering Information
PART MX7839AS TEMP RANGE -40C to +85C PIN-PACKAGE 44 MQFP INL (LSB) 2
Applications
Automatic Test Equipment (ATE) Industrial Process Controls Arbitrary Function Generators Avionics Equipment Minimum Component Count Analog Systems Digital Offset/Gain Adjustment SONET Applications
DUTGNDAB OUTA REFABREFAB+ VDD VSS LDAC A2 A1 A0 CS
1 2 3 4 5 6 7 8 9 10 11
Pin Configuration
TOP VIEW
OUTB OUTC DUTGNDCD OUTD REFCDEFREFCDEF+ VDD OUTE DUTGNDEF OUTF OUTG
44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
DUTGNDGH OUTH REFGHREFGH+ VSS CLR DB12 DB11 DB10 DB9 DB8
MX7839
12
13
14
15
16
17
18
19
20
21
________________________________________________________________ Maxim Integrated Products
WR VCC GND DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7
MQFP
22
Functional Diagram appears at end of data sheet.
1
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +17V VSS to GND ........................................................... -17V to +0.3V VCC to GND ............................................................ -0.3V to +6V A_, DB_, WR, CS, LDAC, CLR to GND .....+0.3V to (VCC + 0.3V) REF_ _ _ _+, REF_ _ _ _-, DUTGND_ _ .................................(VSS - 0.3V) to (VDD + 0.3V) OUT_ ..........................................................................VDD to VSS Maximum Current into REF_ _ _ _ _, DUTGND_ _ ...........10mA Maximum Current into Any Signal Pin ..............................50mA OUT_ Short-Circuit Duration to VDD, VSS, and GND ................1s Continuous Power Dissipation (TA = +70C) 44-Pin MQFP (derate 11.1mW/C above +70C).........870mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient DC Crosstalk REFERENCE INPUTS Input Resistance Input Current REF_ _ _ _+ Input Range REF_ _ _ _- Input Range (REF_ _ _ _+) - (REF_ _ _ _-) Range ANALOG OUTPUTS Output Voltage Swing Resistive Load to GND Capacitive Load to GND DC Output Impedance (Note 1) -10 5 50 0.5 +10 k k pF 0 -5 2 100 1 5 0 10 M A V V V (Note 1) (Note 1) SYMBOL N INL DNL Guaranteed monotonic 2 1 1 0.5 75 10 120 CONDITIONS MIN 13 2 0.9 8 4 TYP MAX UNITS Bits LSB LSB LSB LSB LSB ppm FSR/C V
STATIC PERFORMANCE (ANALOG SECTION)
2
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Input Impedance per DAC Maximum Input Current per DAC Input Range DIGITAL INPUTS Input Voltage High Input Voltage Low Input Capacitance Input Current POWER SUPPLIES VDD Analog Power-Supply Range VSS Analog Power-Supply Range VCC Digital Power Supply Positive Supply Current Negative Supply Current Digital Supply Current PSRR, VOUT / VDD PSRR, VOUT / VSS VDD VSS VCC IDD ISS ICC RL = RL = Digital inputs = 0V or VCC (Note 2) VDD = +15V 5% VSS = -15V 5% 90 90 14.25 -14.25 4.75 8 8 15.75 -15.75 5.25 10 10 0.5 V V V mA mA mA dB dB VIH VIL CIN IIN (Note 1) Digital inputs = 0V or VCC 1 2.4 0.8 10 10 V V pF A -2 SYMBOL CONDITIONS MIN TYP 60 300 +2 MAX UNITS k A V DUTGND_ _ CHARACTERISTICS
MX7839
INTERFACE TIMING CHARACTERISTICS
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, Figure 2a, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER CS Pulse Width Low WR Pulse Width Low LDAC Pulse Width Low CS Low to WR Low CS High to WR High Data Valid to WR Setup Data Valid to WR Hold Address Valid to WR Setup Address Valid to WR Hold CLR Pulse-Activation Time SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 Figure 2b CONDITIONS MIN 50 50 50 0 0 20 0 15 0 300 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns
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3
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
DYNAMIC CHARACTERISTICS
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, RL = 5k, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER Output Settling Time Output Slew Rate Digital Feedthrough Digital Crosstalk Digital-to-Analog Glitch Impulse DAC-to-DAC Crosstalk Channel-to-Channel Isolation Output Noise Spectral Density Note 1: Note 2: Note 3: Note 4: VREF+ = VREF- = 0V (Note 3) (Note 4) SYMBOL CONDITIONS To 0.5 LSB of full scale MIN TYP 31 0.7 0.1 0.2 230 40 99 200 MAX UNITS s V/s nV-s nV-s nV-s nV-s dB nV/Hz
Guaranteed by design. Not production tested. All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at GND or VCC potential. All digital inputs (DB_, A_, WR, CS, LDAC, and CLR) at +0.8V or +2.4V. All digital inputs (DB0 to DB12) transition from GND to VCC with WR = VCC.
Typical Operating Characteristics
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25C, unless otherwise noted.)
INL vs. CODE
MX7839 toc01
DNL vs. CODE
MX7839 toc02
INL AND DNL ERROR vs. TEMPERATURE
0.3 0.2
MX7839 toc03
0.400 0.300 0.200
0.300 0.200 0.100
0.4
ERROR (LSB)
DNL (LSB)
INL (LSB)
0.100 0 -0.100 -0.200 -0.300 -0.400 0 2048 4096 CODE 6144 8192
0.1 0 -0.1 -0.2 INL DNL
0 -0.100 -0.200
-0.3 -0.300 0 2048 4096 CODE 6144 8192 -0.4 -40 -20 0 20 40 60 80 TEMPERATURE (C)
4
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface
Typical Operating Characteristics (continued)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25C, unless otherwise noted.)
ZERO-SCALE AND FULL-SCALE ERROR vs. TEMPERATURE
MX7839 toc04
MX7839
IDD AND ISS vs. TEMPERATURE
MX7839 toc05
DIGITAL SUPPLY CURRENT vs. TEMPERATURE
DIGITAL SUPPLY CURRENT, ICC (A) 24.5 24.0 23.5 23.0 22.5 22.0 21.5 21.0 20.5
MX7839 toc06
1.2 1.0 0.8 0.6 ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -40 -20 0 20 40 60 80 TEMPERATURE (C) FULL SCALE ZERO SCALE
8.0 7.5 7.0 6.5 6.0 5.5 5.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C) IDD
25.0
IDD, ISS (mA)
ISS
20.0 -40 -25 -10 5 20 35 50 65 80 TEMPERATURE (C)
REFERENCE INPUT FREQUENCY RESPONSE
MX7839 toc07
SETTLING TIME vs. CAPACITIVE LOAD
MX7839 toc08
LARGE-SIGNAL STEP RESPONSE
MX7839 toc09
5 0 -5 AMPLITUDE (dB) -10 -15 -20 -25 -30 -35 -40 1k 10k
100 90 80 SETTLING TIME (s) 70 60 50 40 30 20 10 0
REF_ _ _ _ _ = 200mVP-P
LDAC 5V/div
OUT_ 5V/div
100k FREQUENCY (Hz)
1M
10M
10
100
1000
10,000
100,000
10s/div
CAPACITIVE LOAD (pF)
POSITIVE SETTLING TIME
MX7839 toc10
NEGATIVE SETTLING TIME
MX7839 toc11
NOISE VOLTAGE DENSITY vs. FREQUENCY
MX7839 toc12
1000 NOISE VOLTAGE DENSITY (nV/Hz) 100 10
LDAC 5V/div
LDAC 5V/div
OUT_ 1mV/div
OUT_ 1mV/div
10s/div
10s/div
100
1k
10k
FREQUENCY (Hz)
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5
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Typical Operating Characteristics (continued)
(VDD = +15V 5%, VSS = -15V 5%, VCC = +5V 5%, VGND = VDUTGND_ _ = 0, VREF_ _ _ _+ = +5V, VREF_ _ _ _- = -5V, TA = +25C, unless otherwise noted.)
MAJOR CARRY GLITCH IMPULSE (0xOFFF-0x1000)
MX7839 toc13
MAJOR CARRY GLITCH IMPULSE (0x1000-0xOFFF)
LDAC 5V/div
MX7839 toc14
GAIN ERROR vs. VREF (VREF+ - VREF-)
0.8 0.6 GAIN ERROR (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
MX7839 toc15
1.0
LDAC 5V/div
OUT 5mV/div
OUT 5mV/div
2s/div
2s/div
0
2
4 VREF (V)
6
8
10
DNL (MAX, MIN) vs. VREF (VREF+ - VREF-)
MX7839 toc16
ZERO-SCALE ERROR vs. VREF (VREF+ - VREF-)
MX7839 toc17
FULL-SCALE ERROR vs. VREF (VREF+ - VREF-)
0.8 0.6 0.4 FSE (LSB) 0.2 0 -0.2 -0.4
MX7839 toc18
0.5 0.4 0.3 DNL (MAX, MIN) (LSB) 0.2
1.6 1.4 1.2 ZSE (LSB) 1.0 0.8 0.6 0.4 0.2 0 0 2 4 VREF (V) 6 8
1.0
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 2 4 VREF (V) 6 8 10
-0.6 -0.8 -1.0 10 0 2 4 VREF (V) 6 8 10
INL (MAX, MIN) vs. VREF (VREF+ - VREF-)
MX7839 toc19
SHORT-CIRCUIT CURRENT vs. TEMPERATURE
MX7839 toc20
1.0 0.8 0.6 INL (MAX, MIN) (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 2 4 VREF (V) 6 8
30 20 SHORT-CIRCUIT CURRENT (mA) 10 0 -10 -20 -30 -40 FULL-SCALE OUTPUT, SOURCING CURRENT ZERO-SCALE OUTPUT, SINKING CURRENT
10
-40 -25 -10
5
20
35
50
65
80
TEMPERATURE (C)
6
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface
Pin Description
PIN 1 2 3 4 5, 38 6, 29 NAME DUTGNDAB OUTA REFABREFAB+ VDD VSS FUNCTION Device Sense Ground Input for OUTA and OUTB. In normal operation, OUTA and OUTB are referenced to DUTGNDAB. When CLR is low, OUTA and OUTB are forced to the potential on DUTGNDAB. DAC A Buffered Output Voltage Negative Reference Input for DACs A and B Positive Reference Input for DACs A and B Positive Analog Power Supply. Normally set to +15V. Connect both pins to the supply voltage. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. Negative Analog Power Supply. Normally set to -15V. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. Load Input. Drive this asynchronous input low to transfer the contents of the input latches to their respective DAC latches. DAC latches are transparent when LDAC is low and latched when LDAC is high. Address Bit 2 (MSB) Address Bit 1 Address Bit 0 (LSB) Chip Select. Active-low input. Write Input. Active-low strobe for conventional memory write sequence. Input data latches are transparent when WR and CS are both low. WR latches data into the DAC input latch selected by A2, A1, A0 on the rising edge of CS. Digital Power Supply. Normally set to +5V. See the Power Supplies, Grounding, and Bypassing section for bypass requirements. Ground Data Bits 0-12. Offset binary coding. Clear Input. Drive CLR low to force all DAC outputs to the voltage on their respective DUTGND _ _. Does not affect the status of internal registers. All DACs return to their previous levels when CLR goes high. Positive Reference Input for DACs G and H Negative Reference Input for DACs G and H
MX7839
7 8 9 10 11 12
LDAC A2 A1 A0 CS WR
13 14 15-27 28 30 31
VCC GND DB0-DB12 CLR REFGH+ REFGH-
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7
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Pin Description (continued)
PIN 32 33 34 35 36 37 39 40 41 42 43 44 NAME OUTH DUTGNDGH OUTG OUTF DUTGNDEF OUTE REFCDEF+ REFCDEFOUTD DUTGNDCD OUTC OUTB DAC H Buffered Output Voltage Device Sense Ground Input for OUTG and OUTH. In normal operation, OUTG and OUTH are referenced to DUTGNDGH. When CLR is low, OUTG and OUTH are forced to the potential on DUTGNDGH. DAC G Buffered Output Voltage DAC F Buffered Output Voltage Device Sense Ground Input for OUTE and OUTF. In normal operation, OUTE and OUTF are referenced to DUTGNDEF. When CLR is low, OUTE and OUTF are forced to the potential on DUTGNDEF. DAC E Buffered Output Voltage Positive Reference Input for DACs C, D, E, and F Negative Reference Input for DACs C, D, E, and F DAC D Buffered Output Voltage Device Sense Ground Input for OUTC and OUTD. In normal operation, OUTC and OUTD are referenced to DUTGNDCD. When CLR is low, OUTC and OUTD are forced to the potential on DUTGNDCD. DAC C Buffered Output Voltage DAC B Buffered Output Voltage FUNCTION
8
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface
_______________Detailed Description
CLR R R OUT 2R 2R 2R 2R 2R 2R
MX7839
Analog Section
The MX7839 contains eight 13-bit voltage-output DACs. These DACs are inverted R-2R ladder networks that convert 13-bit digital inputs into equivalent analog output voltages, in proportion to the applied reference voltages (Figure 1). The MX7839 has three positive reference inputs (REF_ _ _ _+) and three negative reference inputs (REF_ _ _ _-). The difference from REF_ _ _ _+ to REF_ _ _ _-, multiplied by two, sets the DAC output span. In addition to the differential reference inputs, the MX7839 has four analog-ground input pins (DUTGND_ _). When CLR is high (unasserted), the voltage on DUTGND_ _ offsets the DAC output voltage range. If CLR is asserted, the output amplifier is forced to the voltage present on DUTGND_ _.
D0
D12
D13 DUTGND
REF-
REF+
Figure 1. DAC Simplified Circuit
Reference and DUTGND Inputs
All of the MX7839's reference inputs are buffered with precision amplifiers. This allows the flexibility of using resistive dividers to set the reference voltages. Because of the relatively high multiplying bandwidth of the reference input (188kHz), any signal present on the reference pin within this bandwidth is replicated on the DAC output. The DUTGND pins of the MX7839 are connected to the negative source resistor (nominally 115k) of the output amplifier. The DUTGND pins are typically connected directly to analog ground. Each of these pins has an input current that varies with the DAC digital code. If the DUTGND pins are driven by external circuitry, budget 200A per DAC for load current.
t1 CS t4 t2 WR t8 t9 A0-A2 t5
Output-Buffer Amplifiers
t6 DB0-DB12 t7
t3 t3 LDAC
(NOTE 3)
The MX7839's voltage outputs are internally buffered by precision gain-of-two amplifiers with a typical slew rate of 1V/s. With a full-scale transition at its output, the typical settling time to 1/2 LSB is 31s. This settling time does not significantly vary with capacitive loads less than 10,000pF.
CLR NOTES: 1. ALL INPUT RISE AND FALL TIMES MEASURED FROM 10% TO 90% OF +5V. tr = tf = 5ns. 2. MEASUREMENT REFERENCE LEVEL IS (VINH + VINL) / 2. 3. IF LDAC IS ACTIVATED WHILE WR IS LOW, THEN LDAC MUST STAY LOW FOR t3 OR LONGER AFTER WR GOES HIGH. VOUT_ t10 t10
Figure 2a. Digital Timing Diagram
Figure 2b. Digital Timing Diagram 9
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Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Output Deglitching Circuit
The MX7839's internal connection from the DAC ladder to the output amplifier contains special deglitch circuitry. This glitch/deglitch circuitry is enabled on the falling edge of LDAC to remove the glitch from the R-2R DAC. This enables the MX7839 to exhibit a fraction of the glitch impulse energy of parts without the deglitching circuit. input latches and the DAC latches are transparent when CS, WR, and LDAC are all low. Any change of DB0-DB12 during this condition appears at the output instantly. Transfer data from the input latches to the DAC latches by asserting the asynchronous LDAC signal. Each DAC's analog output reflects the data held in its DAC latch. All control inputs are level triggered. Table 2 is an interface truth table. Input Write Cycle Data can be latched or transferred directly to the DAC. CS and WR control the input latch, and LDAC transfers information from the input latch to the DAC latch. The input latch is transparent when CS and WR are low, and the DAC latch is transparent when LDAC is low. The address lines (A0, A1, A2) must be valid for the duration that CS and WR are low (Figure 2a) to prevent data from being inadvertently written to the wrong DAC. Data is latched within the input latch when either CS or WR is high. Loading the DACs Taking LDAC high latches data into the DAC latches. If LDAC is brought low when WR and CS are low, the DAC addressed by A0, A1, and A2 is directly controlled by the data on DB0-DB12. This allows the maximum digital update rate; however, it is sensitive to any glitches or skew in the input data stream. Asynchronous Clear The MX7839 has an asynchronous clear pin (CLR) that, when asserted, sets all DAC outputs to the voltage present on their respective DUTGND pins. Deassert CLR to return the DAC output to its previous voltage. Note that CLR does not clear any of the internal digital registers. See Figure 2b.
Digital Inputs and Interface Logic
All digital inputs are compatible with both TTL and CMOS logic. The MX7839 interfaces with microprocessors using a data bus at least 13 bits wide. The interface is double buffered, allowing simultaneous updating of all DACs. There are two latches for each DAC (see the Functional Diagram): an input latch that receives data from the data bus, and a DAC latch that receives data from the input latch. Address lines A0, A1, and A2 select which DAC's input latch receives data from the data bus as shown in Table 1. Both the
Table 1. MX7839 DAC Addressing
A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 FUNCTION DAC A input latch DAC B input latch DAC C input latch DAC D input latch DAC E input latch DAC F input latch DAC G input latch DAC H input latch
Table 2. Interface Truth Table
CLR X X X X X 0 LD X X X 0 1 X WR 0 X 1 X X X CS 0 1 X X X X FUNCTION Input register transparent Input register latched Input register latched DAC register transparent DAC register latched Outputs of DACs at DUTGND_ _ Outputs of DACs set to voltage defined by the DAC register, the references, and the corresponding DUTGND_ _
Applications Information
Multiplying Operation
The MX7839 can be used for multiplying applications. Its reference accepts both DC and AC signals. Since the reference inputs are unipolar, the multiplying operation is limited to two quadrants. See the graphs in the Typical Operating Characteristics for dynamic performance of the DACs and output buffers.
Digital Code and Analog Output Voltage
The MX7839 uses offset binary coding. A 13-bit two's complement code is converted to a 13-bit offset binary code by adding 212 = 4096.
1
1
X
X
X = Don't care. 10 ______________________________________________________________________________________
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Table 3. Analog Voltage vs. Digital Code
INPUT CODE 1 1111 1111 1111 1 0000 0000 0000 0 1001 1101 1001 0 0000 0000 0001 0 0000 0000 0000 OUTPUT VOLTAGE (V) +9.997558 0 -3.845215 -9.997558 -10
LSB =
2(REF+ - REF- ) 213
Reference Selection
Because the MX7839 has precision buffers on its reference inputs, the requirements for interfacing to these inputs are minimal. Select a low-drift, low-noise reference within the recommended REF+ and REF- voltage ranges. The MX7839 does not require bypass capacitors on its reference inputs. Add capacitors only if the reference voltage source requires them to meet system specifications.
Note: Output voltage is based on REF+ = +5V, REF- = -5V, and DUTGND = 0V.
Output Voltage Range
For typical operation, connect DUTGND to signal ground, VREF+ to +5V, and VREF- to -5V. Table 3 shows the relationship between digital code and output voltage. The DAC digital code controls each leg of the 13-bit R-2R ladder. A code of 0x0 connects all legs of the ladder to REF-, corresponding to a DAC output voltage (VDAC) equal to REF-. A code of 0x1FFF connects all legs of the ladder to REF+, corresponding to a VDAC approximately equal to REF+. The output amplifier multiplies VDAC by 2, yielding an output voltage range of 2 REF- to 2 REF+ (Figure 1). Further manipulation of the output voltage span is accomplished by offsetting DUTGND. The output voltage of the MX7839 is described by the following equation: DATA VOUT = 2( VREF + - VREF - ) + VREF - 13 2 - VDUTGND where DATA is the numeric value of the DAC's binary input code, and DATA ranges from 0 to 8191 (213 - 1). The resolution of the MX7839, defined as 1 LSB, is described by the following equation:
Minimizing Output Glitch
The MX7839's internal deglitch circuitry is enabled on the falling edge of LDAC. Therefore, to achieve optimum performance, drive LDAC low after the inputs are either latched or steady state. This is best accomplished by having the falling edge of LDAC occur at least 50ns after the rising edge of CS.
Power Supplies, Grounding, and Bypassing
For optimum performance, use a multilayer PC board with an unbroken analog ground. For normal operation, connect the four DUTGND pins directly to the ground plane. Avoid sharing the connections of these sensitive pins with other ground traces. As with any sensitive data-acquisition system, connect the digital and analog ground planes together at a single point, preferably directly underneath the MX7839. Avoid routing digital signals underneath the MX7839 to minimize their coupling into the IC. For normal operation, bypass VDD and VSS with 0.1F ceramic chip capacitors to the analog ground plane. To enhance transient response and capacitive drive capability, add 10F tantalum capacitors in parallel with the ceramic capacitors. Note, however, that the MX7839 does not require the additional capacitance for stability. Bypass VCC with a 0.1F ceramic chip capacitor to the digital ground plane.
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11
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Power-Supply Sequencing
To guarantee proper operation of the MX7839, ensure that power is applied to VDD before VSS and VCC. Also ensure that V SS is never more than 300mV above ground. To prevent this situation, connect a Schottky diode between VSS and the analog ground plane, as shown in Figure 3. Do not power up the logic input pins before establishing the supply voltages. If this is not possible and the digital lines can drive more than 10mA, place current-limiting resistors (e.g., 470) in series with the logic pins.
VSS
VSS VSS MX7839 1N5817
Driving Capacitive Loads
The MX7839 typically drives capacitive loads up to 0.01F without a series output resistor. However, whenever driving high capacitive loads, it is prudent to use a 220 series resistor between the MX7839 output and the capacitive load.
SYSTEM GND
GND
Figure 3. Schottky Diode Between VSS and GND
Chip Information
TRANSISTOR COUNT: 13,225 PROCESS: BiCMOS
12
______________________________________________________________________________________
VDD VSS OUTA
CLR 13 DAC REG A DAC A DATA R REG A 13
DB0- DB12
13
ANALOG POWER SUPPLY
VCC DAC B OUTB
13 DATA REG B DAC REG B
13
13
GND
DIGITAL POWER SUPPLY DUTGNDAB DAC C OUTC
13 DATA REG C DAC REG C
13
13
13 DAC D DATA REG D DAC REG D
13
13 OUTD
13 DAC E
13
13
DUTGNDCD OUTE
ADDRESS DECODE LOGIC 13 DAC F DATA REG F DAC REG F 13 13
DATA REG E
DAC REG E
OUTF
A2 13 DAC G OUTG DATA REG G DAC REG G 13 13 DUTGNDEF
A1
A0
CS 13 DAC H DATA REG H DAC REG H 13 13
WR
OUTH
LDAC MX7839 REFABREFAB+ REFGHREFGH+ REFCDEFREFCDEF+
MX7839
______________________________________________________________________________________
DUTGNDGH
Octal, 13-Bit Voltage-Output DAC with Parallel Interface
Functional Diagram
13
Octal, 13-Bit Voltage-Output DAC with Parallel Interface MX7839
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MQFP44.EPS
PACKAGE OUTLINE 44L MQFP, 1.60 LEAD FORM
21-0826
D
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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